Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems

Luppold, Arno and Kittsteiner, Christina and Falk, Heiko (2016) Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems. In: 19th International Workshop on Software and Compilers for Embedded Systems, 23. - 25. May 2016, St. Goar.

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To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.

Item Type: Conference or Workshop Item (Paper)
Subjects: DBIS Research > Publications
Divisions: Faculty of Engineering, Electronics and Computer Science > Institute of Databases and Informations Systems > DBIS Research and Teaching > DBIS Research > Publications
Depositing User: Frau Christina Kittsteiner
Date Deposited: 10 Jun 2016 18:38
Last Modified: 10 Jun 2016 18:38

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